4Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits
10HiSpMV: Hybrid Row Distribution and Vector Buffering for Imbalanced SpMV Acceleration on FPGAs
21A Composable Dynamic Sparse Dataflow Architecture for Efficient Event-based Vision Processing on FPGA
28Low-Latency, Line-Rate Variable-Length Field Parsing for 100+ Gb/s Ethernet
31REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs
38Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis
57FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAs
61Formal Verification of Source-to-Source Transformations for HLS
64SuperNIC: An FPGA-Based, Cloud-Oriented SmartNIC
65An FPGA-Enabled Framework for Rapid Automated Design of Photonic Integrated Circuits
67POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor Computations
68A Statically and Dynamically Scalable Soft GPGPU
88LevelST: Stream-based Accelerator for Sparse Triangular Solver
111SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff Design Space Exploration
139Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing
141MiCache: An MSHR-inclusive Non-blocking Cache Design for FPGAs
158From Topology to Geometry & Realization in FPGA/VPR Routing
172GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network
182Hardcaml MSM: A High-Performance Split CPU-FPGA Multi-Scalar Multiplication Engine
191Evaluating Versal AI engines for option price discovery in market risk analysis
262A 475 MHz Manycore FPGA Accelerator for RTL Simulation
268CompressedLUT: An Open Source Tool for Lossless Compression of Lookup Tables for Function Evaluation and Beyond
359Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic