Technical Program
All times shown in Pacific Standard Time (UTC-8).
All paper sessions are in TBD, and all poster sessions are in TBD.
Thursday, February 27, 2025
| 09:00 AM-09:10 AM | Opening | |
| 09:10 AM-10:00 AM | Keynote: Architectures for AI Steve Reinhardt (AMD) | |
| 10:00 AM-10:15 AM | Break | |
| 10:15 AM-11:30 AM | Paper Session 1: AI for FPGAs Chair: TBD | |
| FlightVGM: Efficient Video Generation Model Inference with Online Sparsification and Hybrid Precision on FPGAs (Best Paper Candidate) Jun Liu (Shanghai Jiao Tong University), Shulin Zeng (Tsinghua University, Infinigence-AI), Li Ding (Shanghai Jiao Tong University), Widyadewi Soedarmadji (Tsinghua University), Hao Zhou (Shanghai Jiao Tong University), Zehao Wang (Tsinghua University), Jinhao Li (Shanghai Jiao Tong University), Jintao Li (Infinigence-AI), Yadong Dai (Infinigence-AI), Kairui Wen (Infinigence-AI), Shan He (Infinigence-AI), Yaqi Sun (Infinigence-AI), Yu Wang (Tsinghua University), Guohao Dai (Shanghai Jiao Tong University, Infinigence-AI) | ||
| TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient Boosted Decision Trees Alireza Khataei (University of Minnesota), Kia Bazargan (University of Minnesota) | ||
| Greater than the Sum of its LUTs: Scaling Up LUT-based Neural Networks with AmigoLUT Olivia Weng (University of California San Diego), Marta Andronic (Imperial College London), Danial Zuberi (University of California San Diego), Jiaqing Chen (Arizona State University), Caleb Geniesse (Lawrence Berkeley National Laboratory), George A Constantinides (Imperial College London), Nhan Tran (Fermilab), Nicholas Fraser (AMD), Javier Duarte (University of California San Diego), Ryan Kastner (University of California San Diego), Caleb Geniesse (Lawrence Berkeley National Laboratory) | ||
| ReducedLUT: Table Decomposition with “Don’t Care” Conditions (Short Paper) Oliver Cassidy (Imperial College London), Marta Andronic (Imperial College London), Samuel Coward (Intel and Imperial College London), George A. Constantinides (Imperial College London) | ||
| 11:30 AM-12:30 PM | Poster Session 1 | |
| 12:30 PM-01:45 PM | Lunch | |
| 01:45 PM-02:40 PM | Paper Session 2: CAD Chair: TBD | |
| Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA Acceleration Shuoxiang Xu (ShanghaiTech University), Zijian Jiang (Institute of Computing, Chinese Academy of Sciences), Yuxin Zhang (Beijing Insititute of Open Source Chip), David Boland (The University of Sydney), Yungang Bao (ICT/CAS), Kan Shi (Institute of Computing, Chinese Academy of Sciences) | ||
| An Efficient Traversal Method for FPGA Interconnect Resources Based on Regular Routing Wenwei Chen (School of Microelectronics, Fudan University), Lin Ye (School of Microelectronics, Fudan University), XiaoTong Zhao (School of Microelectronics, Fudan University), Tongshu Ding (School of Mathematical Sciences, Fudan University), Jian Wang (School of Microelectronics, Fudan University), Jinmei Lai (School of Microelectronics, Fudan University) | ||
| Two-Phase Transistor Sizing for FPGAs via Bayesian Optimization (Short Paper) Xianfeng Cao (State Key Laboratory of Integrated Chips and Systems, Fudan University), Huizhen Kuang (State Key Laboratory of Integrated Chips and Systems, Fudan University), Yuanqi Wang (State Key Laboratory of Integrated Chips and Systems, Fudan University), Lingli Wang (State Key Laboratory of Integrated Chips and Systems, Fudan University), Yuanqi Wang (State Key Laboratory of Integrated Chips and Systems, Fudan University), xianfeng cao (Fudan University) | ||
| TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platforms (Short Paper) Enlai LI (Hong Kong University of Science and Technology), Zhe LIN (Sun Yat-Sen University), Sharad Sinha (Indian Institute of Technology (IIT) Goa), Wei Zhang (Hong Kong University of Science and Technology) | ||
| 02:40 PM-02:55 PM | Break | |
| 02:55 PM-03:40 PM | Paper Session 3: High Level Synthesis 1 Chair: TBD | |
| ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines (Best Paper Candidate) Jinming Zhuang (Brown University), Shaojie Xiang (Cornell University), Hongzheng Chen (Cornell University), Niansong Zhang (Cornell University), Zhuoping Yang (Brown University), Tony Mao (Cornell University), Zhiru Zhang (Cornell University), Peipei Zhou (Brown University) | ||
| Stream-HLS: Towards Automatic Dataflow Acceleration (Best Paper Candidate) Suhail Basalama (UCLA), Jason Cong (UCLA) | ||
| 03:40 PM-04:00 PM | Break | |
| 04:00 PM-05:00 PM | Paper Session 4: Security Chair: TBD | |
| FAST: FPGA Acceleration of Fully Homomorphic Encryption with Efficient Bootstrapping Zhihan Xu (University of Southern California), Tian Ye (University of Southern California), Rajgopal Kannan (DEVCOM Army Research Office), Viktor K. Prasanna (University of Southern California) | ||
| An FPGA-based Overlay Accelerator for Private Preserving Machine Learning with Homomorphic Encryption Yang Yang (University of Southern California), Rajgopal Kannan (US Army Research Lab), Viktor Prasanna (University of Southern California) | ||
| CIVIC-FPGA: A Trusted FPGA Design Validation by Multi-Tenant Cloud Providers (Short Paper) Yu Feng (University of Florida), Zhaoqi Wang (University of Florida), Christophe Bobda (University of Florida) | ||
| 05:00 PM-06:30 PM | Adjourn & Steering Committee Meeting | |
| 06:30 PM-09:00 PM | Banquet & Panel |
Friday, February 28, 2025
| 09:00 AM-09:10 AM | Chair's Announcement | |
| 09:10 AM-10:00 AM | Keynote: Lessons from 40 years for Reconfigurable Computing John Wawrzynek (University of California, Berkeley) | |
| 10:00 AM-10:15 AM | Break | |
| 10:15 AM-11:15 AM | Paper Session 5: Architecture Chair: TBD | |
| FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis Louis Coulon (EPFL), Lucas Ramirez (EPFL), Jason Anderson (University of Toronto), Mirjana Stojilovic (EPFL), Paolo Ienne (EPFL) | ||
| Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration Endri Taka (The University of Texas at Austin), Ning-Chi Huang (National Yang Ming Chiao Tung University), Chi-Chih Chang (National Yang Ming Chiao Tung University), Kai-Chiang Wu (National Yang Ming Chiao Tung University), Aman Arora (Arizona State University), Diana Marculescu (The University of Texas at Austin) | ||
| Tile-Level Pipeline for Linear Scalable Stencil Computation on AMD AI Engines (Short Paper) Zhenyu Xu (Clemson University), Miaoxiang Yu (Clemson University), Yazhe Zhang (Clemson University), Jillian Cai (Clemson University), Qing Yang (The University of Rhode Island), Tao Wei (Clemson University) | ||
| 11:15 AM-12:15 PM | Poster Session 2 | |
| 12:15 PM-01:30 PM | Lunch | |
| 01:30 PM-02:35 PM | Paper Session 6: High Level Synthesis 2 Chair: TBD | |
| A Unified Framework for Automated Code Transformation and Pragma Insertion Stephane Pouget (University of California, Los Angeles), Louis-Noel Pouchet (Colorado State University), Jason Cong (University of California, Los Angeles) | ||
| Latency Insensitivity Testing for Dataflow HLS Designs Jianyi Cheng (University of Edinburgh), Lianghui Wang (USTC and UCAS), Zijian Jiang (UCAS), Yungang Bao (ICT/CAS), Kan Shi (UCAS), Zijian Jiang (Beijing University of Technology) | ||
| Dynamic Loop Fusion in High-Level Synthesis Robert Szafarczyk (University of Glasgow), Syed Waqar Nabi (University of Glasgow), Wim Vanderbauwhede (University of Glasgow) | ||
| 02:35 PM-02:55 PM | Break | |
| 02:55 PM-04:00 PM | Paper Session 7: Applications Chair: TBD | |
| Heterogeneous, Low-Latency Acceleration of The Virtual Brain on a Versal Adaptive SoC Amirreza Movahedin (Delft University of Technology), Lennart P.L. Landsmeer (Delft University of Technology), Christos Strydis (Erasmus Medical Center), Amirreza Movahedin (Delft University of Technology), Lennart P.L. Landsmeer () | ||
| SAT-Accel: A Modern SAT Solver on a FPGA Michael Lo (University of California, Los Angeles), Mau-Chung Frank Chang (University of California, Los Angeles), Jason Cong (UCLA) | ||
| FPGA-Only Implementation of MIPI C-PHY Receiver Using Blind Oversampling CDR for CMOS Image Sensors Jun Yeon Won (Samsung Electronics), Shinki Jeong (Samsung Electronics), Seongkwan Lee (Samsung Electronics), Minho Kang (Samsung Electronics), Insu Yang (Samsung Electronics), Jaemoo Choi (Samsung Electronics) | ||
| 04:00 PM-04:30 PM | Best Paper Award and Closing Remarks |
Poster Session 1 (February 27)
11:30am – 12:30pm
| Title | Authors |
|---|---|
| wa-hls4ml and lui-gnn: A benchmark and GNN based surrogate model for hls4ml resource and latency estimation | Benjamin Hawks (Fermilab), Dennis Plotnikov (Johns Hopkins University), Nhan Tran (Fermilab), Karla Tame-Narvaez (Fermilab), Mohammad Mehdi Rahimifar (University of Sherbrooke), Hamza Ezzaoui Rahali (University of Sherbrooke), Audrey Corbeil Therrien (University of Sherbrooke), Javier Duarte (UC San Diego), Giuseppe Di Guglielmo (Fermilab), Vladimir Loncar (CERN) |
| InTRRA: Inter-Task Resource-Repurposing Accelerator for Efficient Transformer Inference on FPGAs | Zifan He (University of California, Los Angeles), Hersh Gupta (University of California, Los Angeles), Huifeng Ke (University of California, Los Angeles), Jason Cong (UCLA) |
| DPUV4E: High-Throughput DPU Architecture Design for CNN on Versal ACAP | Guoyu Li (AMD), Pengbo Zheng (AMD), Jian Weng (AMD), Enshan Yang (AMD) |
| Performance Analysis of GEMM Workloads on the AMD Versal Platform | Kaustubh Manohar Mhatre (Arizona State University), Venkata Guru Prasanth Mulleti (Arizona State University), Curt John Bansil (Arizona State University), Endri Taka (The University of Texas at Austin), Aman Arora (Arizona State University) |
| HiGTR: High-Performance FPGA Implementation of Complete GNN-based Trajectory Reconstruction for HEP | Yun-Chen Yang (Department of Electrical & Computer Engineering, National Yang Ming Chiao Tung University, Taiwan), Hsuan-Wei Yu (Department of Electrical & Computer Engineering, National Yang Ming Chiao Tung University, Taiwan), Bo-Cheng Lai (Department of Electrical & Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan), Shih-Chieh Hsu (Department of Physics, University of Washington, USA), Mark Neubauer (Department of Physics, University of Illinois at Urbana-Champaign, USA), Santosh Parajuli (Department of Physics, University of Illinois at Urbana-Champaign, USA) |
| FPGA Implementation of a 1D-CNN Modulation Classifier for Radar Signals | Edgard Cansio (Brazilian Navy Research Institute), Edgard Cansio (Brazilian Navy Research Institute) |
| RRNS Arith Lib: An Open-Source Redundant Residue Number System Arithmetic VHDL Library | Tim Oberschulte (Institute of Microelectronic Systems, Leibniz University Hannover), Enno Sievers (), Holger Blume (Institute of Microelectronic Systems, Leibniz University Hannover) |
| Resource Scheduling for Real-Time Machine Learning | Suyash Vardhan Singh (University of South Carolina), Iftakhar Ahmad (University of South Carolina), David Andrews (University of Arkansas), Miaoqing Huang (University of Arkansas), Austin Downey (University of South Carolina), Jason D. Bakos (University of South Carolina) |
| BAQET: BRAM-aware Quantization for Efficient Transformer Inference via Stream-based Architecture on a FPGA | Ling-Chi Yang (National Yang Ming Chiao Tung University), Chi-Jui Chen (Graduate Degree Program of College of Electrical and Computer Engineering in National Yang Ming Chiao Tung University), Trung Le (Electrical and Computer Engineering in University of Washington), Bo-Cheng Lai (Department of Electrical & Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan), Scott Hauck (University of Washington), Shih-Chieh Hsu (University of Washington, Dept. of Physics) |
| Neural Network Inference in High-Performance Computing: Closing the Gap for Reconfigurable Accelerators in Data Centers | Linus Jungemann (Paderborn Center for Parallel Computing / Paderborn University), Bjarne Wintermann (Paderborn Center for Parallel Computing / Paderborn University), Heinrich Riebler (Paderborn University), Christian Plessl (Paderborn University) |
| An Empirical Comparision of LLM-based Hardware Design and High-level Synthesis | Fan Cui (School of Integrated Circuits, Peking University), Youwei Xiao (Peking University), Kexing Zhou (Peking University), Yun Eric Liang (Peking University) |
| FPGA-Oriented Design Space Exploration of a Real-Time Road Scene Semantic Segmentation Deep Neural Network | Hugo Le Blevec (IMT Atlantique), Mathieu Léonardon (IMT Atlantique), Stefan Weithoffer (IMT Atlantique), Matthieu Arzel (IMT Atlantique) |
| FMC-LLM: Enabling FPGAs for Efficient Batched Decoding of 70B+ LLMs with a Memory-Centric Streaming Architecture | Wenheng Ma (Tsinghua University, Infinigence-AI), Xinhao Yang (Tsinghua University, Infinigence-AI), Shulin Zeng (Tsinghua University, Infinigence-AI), Tengxuan Liu (Tsinghua University, Infinigence-AI), Libo Shen (The Chinese University of Hong Kong), Hongyi Wang (Tsinghua University, Infinigence-AI), Shiyao Li (Tsinghua University, Infinigence-AI), Jiewen Wang (Infinigence-AI), Yuhan Zhang (Infinigence-AI), Hao Guo (Infinigence-AI), Jintao Li (Infinigence-AI), Ziming Zhang (Tsinghua University), Zhenhua Zhu (Tsinghua University), Xuefei Ning (Tsinghua University), Tsung-Yi Ho (The Chinese University of Hong Kong), Guohao Dai (Shanghai Jiao Tong University, Infinigence-AI), Yu Wang (Tsinghua University), Wenheng Ma (Tsinghua University), Tsung-Yi Ho (The Chinese University of Hong Kong) |
Poster Session 2 (February 28)
11:30am – 12:30pm
| Title | Authors |
|---|---|
| Enhancing FPGAs with Analog In-Memory Computing Macros | Archit Gajjar (Hewlett Packard Labs), Lei Zhao (Hewlett Packard Labs), Omar Eldash (Hewlett Packard Labs), Aishwarya Natarajan (Hewlett Packard Labs), Rand Jean (Hewlett Packard Labs), Xia Sheng (Hewlett Packard Labs), Giacomo Pedretti (Hewlett Packard Labs), Paolo Faraboschi (Hewlett Packard Labs), Jim Ignowski (Hewlett Packard Labs), Luca Buonanno (Hewlett Packard Labs) |
| ART: Accelerator Customization for Real-Time Systems | Shixin Ji (Brown University), Xingzhen Chen (Brown University), Wei Zhang (Brown University), Zhuoping Yang (Brown University), Jinming Zhuang (Brown University), Sarah Schultz (Brown University), Yukai Song (University of Pittsburgh), Jingtong Hu (University of Pittsburgh), Alex K. Jones (Syracuse University), Zheng Dong (Wayne State University), Peipei Zhou (Brown University) |
| PipeLink: a pipelined resource sharing system for dataflow high-level synthesis | Rui Li (Intel), Lincoln Berkley (Yale University), Rajit Manohar (Yale University) |
| High Throughput Low Latency Network Intrusion Detection on FPGAs: a Raw Packet Approach | Muhammad Ali Farooq (Arizona State University), Abid Rafique (National University of Sciences and Technology), Suhaib A Fahmy (King Abdullah University of Science and Technology), Aman Arora (Arizona State University) |
| IceSpy: Reconfigurable Edge Accelerator for Scalable and Private Structural Health Monitoring | Jonathan (Ta), Sang-Woo Jun (UC Irvine) |
| HEDWIG: Homomorphic Encryption Accelerator Design Using BFV-HPS With HiGh-Speed Fixed-Point Approximation | Antian Wang (Purdue University, Fort Wayne), Weihang Tan (ScaleFlux), Zhenyu Xu (Clemson University), Tao Wei (Clemson University), Caiwen Ding (University of Minnesota Twin Cities), Keshab K. Parhi (University of Minnesota), Yingjie Lao (Tufts Univeristy) |
| Seamless acceleration of Fortran intrinsics via AMD AI engines | Nick Brown (EPCC, University of Edinburgh), Gabriel Rodriguez-Canal (University of Edinburgh) |
| No Time to Lose: Enabling Real-Time Fluorescence Lifetime Imaging on Resource-constrained FPGAs Through Efficient Scheduling | Ismail Erbas (Rensselaer Polytechnic Institute), Aporva Amarnath (IBM Research), Vikas Pandey (Rensselaer Polytechnic Institute), Karthik Swaminathan (IBM Research), Naigang Wang (IBM Research), Xavier Intes (Rensselaer Polytechnic Institute) |
| ReducedLUT: Table Decomposition with “Don’t Care” Conditions (Short Paper) | Oliver Cassidy (Imperial College London), Marta Andronic (Imperial College London), Samuel Coward (Intel and Imperial College London), George A. Constantinides (Imperial College London) |
| Two-Phase Transistor Sizing for FPGAs via Bayesian Optimization (Short Paper) | Xianfeng Cao (State Key Laboratory of Integrated Chips and Systems, Fudan University), Huizhen Kuang (State Key Laboratory of Integrated Chips and Systems, Fudan University), Yuanqi Wang (State Key Laboratory of Integrated Chips and Systems, Fudan University), Lingli Wang (State Key Laboratory of Integrated Chips and Systems, Fudan University), Yuanqi Wang (State Key Laboratory of Integrated Chips and Systems, Fudan University), xianfeng cao (Fudan University) |
| TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platforms (Short Paper) | Enlai LI (Hong Kong University of Science and Technology), Zhe LIN (Sun Yat-Sen University), Sharad Sinha (Indian Institute of Technology (IIT) Goa), Wei Zhang (Hong Kong University of Science and Technology) |
| CIVIC-FPGA: A Trusted FPGA Design Validation by Multi-Tenant Cloud Providers (Short Paper) | Yu Feng (University of Florida), Zhaoqi Wang (University of Florida), Christophe Bobda (University of Florida) |
| Tile-Level Pipeline for Linear Scalable Stencil Computation on AMD AI Engines (Short Paper) | Zhenyu Xu (Clemson University), Miaoxiang Yu (Clemson University), Yazhe Zhang (Clemson University), Jillian Cai (Clemson University), Qing Yang (The University of Rhode Island), Tao Wei (Clemson University) |